Wafer map pattern recognition. CNN can improve the accuracy, but the drawback is the expensive computation cost. This research work seeks to address the pattern recognition task for the identification of defects in wafer maps, by developing a deep Convolutional Neural Network (CNN) classifier. The former refers to wafer maps that host only one defect pattern, while the latter refers to wafer maps in which two or more defect pat-terns co-exist. Sep 20, 2021 · This research work seeks to address the pattern recognition task for the identification of defects in wafer maps, by developing a deep Convolutional Neural Network (CNN) classifier that achieves 95. Oct 1, 2021 · The effectiveness of the proposed method has been verified from following three aspects from a real-world data set of wafer maps(WM-811K): salient defect pattern recognition accuracy up to 94. A big challenge for these methods is whether the extracted features can effectively separate various patterns exhibiting on wafer maps. Google Scholar Cross Ref Feb 1, 2015 · A wafer defect pattern recognition and analysis method based on convolutional neural network and it turns out that the appropriate dimensionality reduction can increase the accuracy and speed of wafer map retrieval. Moreover, the accuracy of our method using a small amount of supervised data for defect pattern recognition is far higher than that of full supervised model recognition. use the method of decision-level information entropy fusion to realize the final classification of the wafer map. Jul 18, 2022 · Through the efficient recognition of the wafer map failure pattern type, the semiconductor manufacturing process and its product performance can be improved, as well as reducing the product cost. Consequently, there has been a surge in the application of machine learning, a series of algorithms capable of learning patterns within data distributions, 14 for defect pattern recognition on WBMS. In our study, a local property analysis-based approach is proposed for wafer map failure pattern recognition. We represented the label of each wafer map as a 9-dimensional one-hot vector. The main aim of this study is to learn general-purpose representations of wafer maps so that they can be used for various downstream tasks. The wafer map used to train a Minion is called its anchor. 32, no. In this study, we propose a deep convolutional neural network architecture incorporating improved convolutional block attention module (I-CBAM) for pattern recognition and classification of single-type wafer map defects. Google Scholar Size: 30STDFs (121MB), DB size: ~ 4GB, 250 tables. We collected a large amount of wafer map data in a wafer manufacturing plant. As a result, the process is less error-prone. 2806931. The classification performance depends significantly on the Oct 1, 2016 · The effectiveness of the proposed method has been verified from following three aspects from a real-world data set of wafer maps(WM-811K): salient defect pattern recognition accuracy up to 94. R. 4, pp. 2014. Abstract. The distribution of defect categories was extremely imbalanced. 0%), and computation time has a significantly reduction. 3% Sep 28, 2022 · The combination of feature extraction and classification methods is an often used approach for wafer map failure pattern recognition. In this paper, a focal auxiliary classifier generative adversarial network (FAC-GAN) for defective wafer pattern recognition with imbalanced data is proposed. -Y. Nov 7, 2023 · In semiconductor manufacturing, patterns formed by defective dies in a wafer bin map (WBM) reveal possible problems during the wafer fabrication process. This paper proposes a WBM defect pattern inspection strategy based on the DenseNet deep learning model, the structure and training loss function are improved according to the characteristics of the WBM Apr 1, 2023 · Wafer map pattern analysis. In this graph, every node is a wafer map. 3% This method introduces a hybrid self-attention module into the feature embedding network that helps to automatically learn the global dependence of channels and positions in the wafer map to obtain more discriminative features. A wafer map contains a graphical representation of the locations about defect pattern on the semiconductor wafer, which can provide useful information for quality engineers. Sections. 3% accuracy and 93. MYSQL database. 2364237 Google Scholar; Xu D Tian Y A comprehensive survey of clustering algorithms Annals of Data Science 2015 2 2 165 193 10. Among them, 0 stands for the back-ground, 1 stands for normal dies, and 2 stands for defective dies. Our solution brings together different aspects of the Spotfire analytics stack to solve this tricky problem. 16 proposed a DCNN model with wafer map pattern recognition accuracy of 99. Accurately identifying defect patterns in wafer maps can help engineers find abnormal failure factors in production lines. Mar 24, 2023 · Manufacturing wafers is an intricate task involving thousands of steps. The second step is to create pre-trained convolutional neural networks for single-type pattern classification. This study presents a novel convolutional neural network (CNN)–based method to automatically recognize the defect pattern on wafer maps that uses polar mapping before the training of CNN to transform the circular wafer map into a matrix, which can be processed within CNN architecture. In that regard, data-driven approaches have been actively studied in the literature for efficient analysis and can be categorized into two main approaches: clustering and classification. Widely available robust database with extensive technical help and online information available. Secondly, I-CBAM is integrated into the ResneXt50 backbone network as a feature extraction network. MixedWM38 Dataset (WaferMap) has more than 38000 wafer maps, including 1 normal pattern, 8 single defect patterns, and 29 mixed defect patterns, a total of 38 defect patterns. The deep convolutional neural network (DCNN) is the most effective algorithm in wafer defect pattern analysis. Therefore, this paper proposes an accurate model for the Mar 14, 2023 · The work in implemented a wafer map pattern recognition flow and experimented with 8300 wafer maps from an automotive product line. Apr 1, 2023 · Third, the different rotations of each wafer map are close to each other for both the unlabeled and labeled wafer maps. Jang, and Jui-Long Chen. These wafer maps are obtained by testing the electrical performance of each die on the wafer through test probes. An excellent inspection algorithm can improve the production efficiency and yield. , Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets, IEEE Transactions on Semiconductor Manufacturing 28 (2015) 1 – 12, 10. 2018. In literature, different approaches have been proposed to ad- Feb 17, 2022 · Wafer map inspection is essential for semiconductor manufacturing quality control and analysis. https://doi. (2)run MulSource. The effectiveness of the proposed method is demonstrated for various downstream tasks related to wafer map pattern analysis: visualization, clustering, retrieval, and classifier training. 2364237 View PDF View article Google Scholar May 1, 2013 · Wafer map defect pattern recognition and classification can locate the cause of failures in the manufacturing process. (2002) outline that special shapes appearing on the defect map pattern may come from the machine or process, according to different map patterns, then can find out the root of problems. In this paper, we propose a novel methodology for wafer map defect pattern classification using deep selective learning. In semiconductor manufacturing, wafer map pattern analysis is crucial for examining the root causes of process failures. Mar 1, 2019 · DNN is widely used in wafer map related studies because it is suitable for pattern recognition application and wafer maps can be treated as images [5]. These wafer maps are obtained by testing the electrical performance of each die on the wafer through test The wafer dataset can be augmented by using a simple convolutional autoencoder model. 3% and the accuracy of some types has an obvious improvement, multi-patterns recognition accuracy(82. Although various deep learning-based approaches have been proposed for automated defect pattern classification, they often demand a large amount of labeled data for effective training. More speci cally, we use state-of-the-art deep learning object detection model, YOLO, which can localize and classify defects in two-dimensional wafer map images. In this paper, we proposed a decision tree ensemble Jan 1, 2023 · The inclusion criteria include: (i) papers published between the 1st of January 2017 and the 15th of May 2022 (date of literature search)); (ii) the process of defect detection in wafer maps; (iii) AI-based algorithms, including both traditional ML and DL techniques incorporated for defect pattern recognition; (iv) ML-based methods in wafer image corresponds to a defect on the wafer. Building a classification model is a primary challenge owing to the high cost of labeling wafer maps with their defect categories to create a training dataset. To increase the productivity, it is important to manage yield and reduce defects in the semiconductor industry. 2. However, manual labeling is a costly and time-consuming process that . Citations: 5. The wafer map may not only reveal a specific defect pattern for engineering trouble shooting but also provide an opportunity for process control, test optimization, quality improvement. Dec 22, 2022 · R. Analyzing the spatial defect patterns of previously processed wafers is a key step in identifying the root causes of yield degradation. With the continuous drive toward integrated circuits scaling, efficient yield analysis is becoming more crucial yet more challenging. 2024. Dec 1, 2021 · Automation of wafer map pattern classification has been an active research topic for identifying the root causes of semiconductor manufacturing processes. Y. Failure patterns exhibit the information related to defect generation mechanisms. In semiconductor manufacturing, statistical quality control hinges on an effective analysis of wafer bin Defective wafer pattern recognition is important for quality control and yield enhancement in semiconductor fabrication systems. Hence, the identification of these defect patterns helps the early detection and diagnosis of the faults. The final step is to determine whether the patterns on wafer maps are mixed based probabilities on softmax function. , Lee J. Many engineers inspect the quality of each chip and check the defect pattern on the wafer bin maps. However, because increasingly more Mar 1, 2008 · Download Citation | On Mar 1, 2008, Shu Fan Liu and others published Wavelet Transform Based Wafer Defect Map Pattern Recognition System in Semiconductor Manufacturing | Find, read and cite all Oct 17, 2020 · Wafer map defect detection and recognition using joint local and nonlocal linear discriminant analysis. Analyzing and classifying defective information on the wafer map aids in defect source Wafer map pattern recognition is instrumental for detecting systemic manufacturing process issues. Source: Deformable Convolutional Networks for Efficient Mixed-Type Wafer Defect Pattern Recognition. Wafer maps can exhibit specific failure patterns that provide crucial details for 2021a, 2021b) becomes to be used for wafer map pattern classification. H. 26% for the WM-811K dataset. Recently, a few research groups have processed large-scale wafer map datasets accurately and efficiently using some novel techniques Jan 18, 2018 · Wafer maps provide important information for engineers in identifying root causes of die failures during semiconductor manufacturing processes. , traditional classification based and deep learning based approaches. One of the efforts is to identify defect patterns and control the cause factors that affects the defects. This paper reconsiders the causes of Sep 28, 2022 · A method for wafer map defect pattern recognition was proposed in 9 by combining geometry-based and radon-based feature extraction, and then the SVM classifier was applied to classify the defect We propose an automatic wafer defect maps detection method based on unsupervised learning. Wafer defect pattern recognition and analysis based on convolutional neural network. The collected wafer maps are usually imbalanced, which may degrade the performance of classifier. Wang and N. Traditionally, wafer inspection was performed by experienced engineers who can identify the failure cause based on the wafer defect pattern. (2) Pattern recognition of defects in wafer drawing is very important to determine the root cause of production defects, which can provide insights for the production improvement of wafer plants. Traditional DCNNs rely heavily on high quality datasets for training. In wafer manufacturing process, there will be mixed defects, detection of mixed defects is much more complex. Nov 1, 2023 · Each wafer map had a single defect pattern belonging to one of the following defect categories: Center, Donut, Edge-Local, Edge-Ring, Local, Random, Scratch, Near-Full, and None. Nov 6, 2023 · Wafers are products in semiconductor manufacturing and serve as the foundation for producing semiconductor chips. The accurate classification of failure patterns in wafer maps can provide crucial information for engineers to recognize the causes of the fabrication problems. Conventional approaches of wafer map Apr 1, 2024 · This paper proposes an efficient deep learning framework designed explicitly for mix-type wafer map defect pattern recognition that incorporates several crucial design elements, including lightweight convolutions, bottleneck residual connections, efficient channel attention mechanisms, and optimized activation functions. Spatial pattern recognition: besides defect clusters, the spatial pattern of the defects usually provides a good approach to wafer problem solving. Feb 1, 2015 · A set of novel rotation- and scale-invariant features is proposed for obtaining a reduced representation of wafer maps and shows that the proposed features and overall system can process large-scale data sets effectively and efficiently, thereby meeting the requirements of current semiconductor fabrication. This dataset contains 38,015 wafer maps with a size of (52, 52). For every pair of wafer maps, we can therefore perform mutual recognition, which results in a recognition graph. Feature engineering and dimension most to yield loss, and for that, wafer map analysis is a key. Dec 1, 2021 · The systematic failure pattern recognition method for wafer map classification based on multi-source and two-channel convolutional neural network is explored. 1007/s40745-015-0040-1 Jan 5, 2024 · Wafer bin maps (WBMs) data, presented as images, play a critical role in identifying defects in the semiconductor industry. Tools. e. Available for download on the Spotfire Exchange, the Wafer Pattern Detection Dashboard for Spotfire® can get you started. Defect detection on wafers holds immense significance in producing micro [10] Wu M. (2019a). PDF. We proposed a contrastive learning framework for semi-supervised learning and prediction of wafer map Oct 19, 2021 · Wafer maps provide engineers with important information about the root causes of failures during the semiconductor manufacturing process. Therefore, the identification of these patterns is important for root cause diagnosis and yield enhancement. During the wafer testing stage, functional and electrical parameters are examined to identify defects in chip design and fabrication. To accurately Wafermap Defect Pattern Recognition. Nov 1, 2023 · Wafer bin maps (WBMs), which represent the spatial distribution of defective dies on the wafer, may contain specific defect patterns that offer useful insight into the underlying causes of anomalies in the processes. The joint requirement is noise filtering and identical input dimension size. eswa. 1109/tsm. 596--604, 2019. Info. Each NN recognizer is called a Minion. Recently, as the manufacturing process becomes increasingly complicated, mixed-type defect patterns have been frequently observed on Jun 1, 2020 · Engineering, Computer Science. " Wafer map defect pattern recognition provides a visual way for root cause analysis and yield learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. However, DNN is more suitable for large Nov 15, 2023 · In this section, in order to improve the classification accuracy of wafer defect pattern recognition, a deep convolutional neural network model combined with an improved attention mechanism is proposed. Apr 6, 2024 · Consequently, there exists a potential to establish a connection between defect types and abnormal processing environments in wafer maps, giving rise to wafer map defect pattern recognition. As shown in Figure 5, 10 10 raw data are used to generate a wafer map, which is a Centre defect pattern. "Wafer map failure pattern recognition and similarity ranking for large-scale data sets. This study tries to improve WMDPI and classification based on the DCNN idea and add residual Nov 1, 2023 · Defect pattern recognition (DPR) of wafer maps can be essential as the accurate classification helps with the fabrication process improvement and thus avoiding further defects. Oct 6, 2023 · As the globalization of semiconductor design and manufacturing processes continues, the demand for defect detection during integrated circuit fabrication stages is becoming increasingly critical, playing a significant role in enhancing the yield of semiconductor products. Through the efficient recognition of the wafer map failure pattern type, the semiconductor manufacturing process and its product performance can be improved, as well as reducing the product cost. org/10. 2364237. , Byun J. In this paper, we will survey the recent pace of progress on advanced methodologies for wafer failure pattern recognition, especially for mixed-type one. This Feb 4, 2020 · Defect clusters on the wafer map can provide important clue to identify the process failures so that it is important to accurately classify the defect patterns into corresponding pattern types. As a result, test quality, reliability and yield could be improved accordingly. , Jang J. , Jin C. Ken et al. IEEE Transactions on Semiconductor Manufacturing, 29(1), 33–43. We present a method for wafer map defect pattern classification and image retrieval using convolutional neural networks (CNNs). The manufacturing yield of semiconductor under silicon technology depends heavily on wafer processing. The wafer map is the result of the wafer testing process. To get the accurate and consistent classification results regardless of the MixedWM38. The main method steps are as follows: (1) First, the convolutional block attention module (CBAM) (Woo, Park, Lee, & Kweon, 2018) is improved Nov 1, 2023 · This article proposes a new framework to segment different defect patterns on the wafer map by using a semantic segmentation approach, which works well on single and known and unknown mixed types. This model is an end-to-end 19-layer network, which can Sep 28, 2022 · The combination of feature extraction and classification methods is an often used approach for wafer map failure pattern recognition. 123914 Corpus ID: 268989549; Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition @article{Piao2024AntecedentHM, title={Antecedent hash modality learning and representation for enhanced wafer map defect pattern recognition}, author={Minghao Piao and Cheng Hao Jin and Baojiang Zhong}, journal={Expert Systems with wafer map. However, such process is tedious and an automated alternative is desired [2,3]. Wafer test Sep 22, 2021 · Wafer bin map (WBM) inspection is a critical approach for evaluating the semiconductor manufacturing process. This paper applies artificial intelligence based pattern recognition techniques to distinguish fab-induced defects from test-induced ones. Whenever the wafer test result of a WUT is available, it can be compared immediately with existing clusters. Google Scholar and Its Impact on Mixed-type Spatial Pattern Recognition in Wafer Bin Maps Ahmed Aziz Ezzat, Member, IEEE, Sheng Liu, Dorit Hochbaum, and Yu Ding, Senior Member, IEEE Abstract—Statistical quality control in semiconductor man-ufacturing hinges on effective diagnostics of wafer bin maps, wherein a key challenge is to detect how defective chips Oct 1, 2021 · The traditional defect classification method firstly extracts the features from wafer maps, and then uses them as inputs of the classifier to perform pattern recognition (Koo and Cho, 2010). In this research, we present an image-based wafer map defect pattern classification method. Mixed-type DPR is much more complicated compared to single-type DPR due to varied spatial features, the uncertainty of defects, and the number of defects present. During fabrication Jun 1, 2023 · 3. However, as the processes become increasingly complicated, various single-type defect patterns may emerge and be coupled on a wafer and thus shape a mixed-type pattern. The metric classifier is used for classification to realize the pattern recognition of wafer defects in small samples. , without performing feature extraction). Expand. 2. However, obtaining balanced and sufficient labeled data is difficult in practice. Predictive modeling approaches have been successful in automated wafer map pattern classification. , Xu, Q. Motivation：. The experiment divided the wafer maps into two batches, the first batch with the first 50 wafer lots and the second batch with the remaining wafer lots. Recent research applying deep learning to the field of defect pattern recognition in wafer maps has greatly accelerated the process of defect detection. Each wafer map is labeled with one of 38 defect patterns: normal (non-defect), 8 single-defects, 13 2-mixed-defects, 12 3-mixed-defects, and 4 4-mixed-defects. However, because these methods are of low accuracy, they are not good enough for large-scale dataset analyses. "IEEE Transactions on Semiconductor Manufacturing28. Defect Pattern Recognition (DPR) of wafer maps is crucial to find the root cause of the issue and further improving the yield in the wafer foundry. , 2018 Piao M. ), ICAART 2020 - Proceedings of the 12th International Conference on Agents and Artificial Intelligence (pp. The first step is to initialize the weights with the convolutional autoencoder. TLDR. Clustering algorithm is developed to subdivide defect map images into several regions. 1016/j. Expand Aug 23, 2022 · Mixed pattern recognition methodology on wafer maps with pre-trained convolutional neural networks. Twenty eight thousand six hundred synthetic wafer maps for 22 defect classes are generated theoretically and used for CNN The accurate and automatic inspection of wafer maps is vital for semiconductor engineers to identify defect causes and to optimize the wafer fabrication process. Figure 1(a-b) show examples of single-type defect patterns, whereas Figure 1(c) depicts a mixed May 8, 2023 · There are mainly two types of wafer map failure pattern recognition, i. However, the task of labeling and classifying WBM data, which are generated daily in the tens of thousands or more, presents a challenge for experts This work proposes to use a graph-theoretic method called adjacency-clustering, which leverages spatial dependence among adjacent defective chips to effectively filter the raw wafer bin maps, and finds that the margin of improvement appears to be a function of the defect pattern complexity. 1 (2014): 1-12. 1 - 12 , 10. In order to achieve the high accuracy of pattern recognition, noise elimination procedure is necessary to remove the isolated defects and thus enhances the quality of defect maps in image format. The proposed CNN-based model utilizes various pre Two different wafer map as input to CNN experimentData = 1, Use original wafer map as input of CNN experimentData = 2, Use the wafer Use the wafer after graying and median filtering as the input of CNN. 1049/cit2. Insertion duration: Approx ~ 10‐15mins per STDF. Currently analytical Wafer Map Failure Pattern Recognition and Similarity Ranking Oct 8, 2021 · We propose a new pattern recognition method for wafer surface defects based on unsupervised learning to reduce the human impact and labor cost caused by manual supervision. Traditional machine learning methods have historically paved the way in this domain. Two nodes have an edge connecting them if their recognizer recognizes each other Jul 19, 2022 · Wafermap Pattern Recognition. Recently, the convolutional neural network (CNN) method is used to raw wafer map data without feature extraction. Rocha, L. Thus, accurately classifying WBM defect patterns is essential to maintain high quality and enhance the overall yield. , & Wang, H. Jul 19, 2022 · First published: 19 July 2022. Wafer maps can exhibit specific failure patterns that provide crucial details for assisting engineers in identifying the cause of wafer pattern failures. 974–979). Trying to catch and understand defect/failure patterns can be quite challenging. Transfer learning is beneficial when the size of training data is small. 78% macro F1-score. Traditional classification usually needs feature engineering, and deep learning requires lower human intervention and feature engineering. 1 - 12 CrossRef Google Scholar In the SPR literature, defect patterns in wafer bin maps can either be single-type or mixed-type. Share. Steels, & J. We extracted three types of local property-based features from the wafer maps. Article Google Scholar Yu, N. van den Herik (Eds. YOLO is a one-stage object detector, which is fast and accurate. As the integrated circuits process becomes more and more complex with the technology scaling, improving the ability to recognize the defect patterns of the wafer maps is required [2]. Chen, "Wafer map defect pattern recognition using rotation-invariant features," IEEE Transactions on Semiconductor Manufacturing, vol. Grid is a repeating defect pattern that appears in multiple wafers, so identifying such patterns helps to trace the root cause of defects Dec 15, 2022 · A deep convolutional neural network (DCNN) model which includes the convolutional layer, batch normalization layer, Relu layer, maximum pooling layer, full connection layer, Softmax layer and classification layer is established for the problem of failure pattern recognition of wafer map. Apr 1, 2023 · Kong and Ni (2020) adapted a semi-supervised VAE for wafer map pattern classification. However, high cost in labeling wafer patterns renders it impossible to leverage large amounts of valuable unlabeled data in conventional machine learning based wafer map pattern prediction. A deep convolutional neural network model is established for the problem of fault pattern recognition of wafer map. Dec 22, 2023 · Wafer bin map (WBM) defect patterns play a crucial role in identifying the root cause of manufacturing defects in the semiconductor industry. Traditional wafer map defect pattern detection methods involve manual inspection using electron microscopes to collect Therefore, defect pattern recognition (DPR) and automatic pattern classification (ADC) is critical to improve yield and productivity. A wafer map deep clustering (WMDC) model that learns generic representations from unlabeled datasets in an unsupervised manner and improves the recognition accuracy of the model when trained using scarce labeled data by transferring the weights of unsupervised pretraining. 1109/TSM. Sep 18, 2020 · The enhancement of production yield is a continuous challenge in semiconductor manufacturing. Previously, Shawon et al. However, when different defects are mixed on Feb 1, 2015 · Wafer maps can exhibit specific failure patterns that provide crucial details for assisting engineers in identifying the cause of wafer pattern failures. Apr 1, 2024 · DOI: 10. Defect pattern recognition (DPR) of wafermap, especially the mixed-type defect, is critical for determining the root cause of production defect. Our proposed approach features an integrated reject option where the model chooses to abstain from predicting a class label when Nov 30, 2021 · Wafer map failure pattern recognition and similarity ranking for large-scale data sets IEEE Transactions on Semiconductor Manufacturing , 28 ( 2014 ) , pp. Conventional approaches of wafer map failure pattern recognition (WMFPR) and wafer map similarity ranking (WMSR) generally involve applying raw wafer map data (i. 22M records, 16850 results, 32 sec. However, when different defects are mixed on the same wafer, the mixed type is very complex, and it is still difficult to recognize the defect pattern. Sql query : 10. If the wafer map matches one Sep 10, 2021 · The proposed model called Opt-ResDCNN is a unique model which combines the concept from the DCNN model and residual blocks. Various defect patterns occur due to increasing wafer sizes and decreasing features sizes, which makes it very complex and unreliable process to identify them. . , Chen J. [2] Fan, Mengying, Qin Wang, and Ben van der Waal. In A. We employ advanced deep learning approaches to localize and classify wafer defects based on annotating images with labels. FAC-GAN is Apr 1, 2023 · Piao et al. Deep learning method has become a good choice to solve the problem of complex pattern There were a great many early studies investigating wafer map failure pattern recognition (WMFPR) [5-8]. 15 For example, Baly and Hajj 16 suggested employing support vector Nov 15, 2023 · Firstly, a multi-branch channel attention mechanism is designed to focus on the main defect pattern of the wafer map, extract richer features, and identify different types of defect clusters more accurately. The presented method consists of two main steps: without any specific preprocessing, high-level features are The effectiveness of the proposed method has been verified from following three aspects from a real-world data set of wafer maps(WM-811K): salient defect pattern recognition accuracy up to 94. Aug 23, 2022 · Wu M-J Jang J-SR Chen J-L Wafer map failure pattern recognition and similarity ranking for large-scale data sets IEEE Transactions on Semiconductor Manufacturing 2015 28 1 1 12 10. May 19, 2023 · Wafer map defect pattern classification is essential in semiconductor manufacturing processes for increasing production yield and quality by providing key root-cause information. Dec 15, 2023 · The MixedWM38 dataset () was used to demonstrate the effectiveness of the proposed method. m. Specially, recognizing grid, including line and intersection point types in wafer defect patterns is a challenging problem for process and test engineers. Most studies on wafer map pattern analysis have presented methods specialized for clustering and classification tasks. In our study, we have extracted local property analysis based Apr 22, 2024 · The digitization of semiconductor manufacturing processes has led to the accumulation of a substantial volume of wafer data. Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. Feb 16, 2018 · Wafer maps contain information about defects and clustered defects that form failure patterns. Nov 30, 2023 · Wafer map failure pattern recognition and similarity ranking for large-scale data sets IEEE Transactions on Semiconductor Manufacturing , 28 ( 1 ) ( 2015 ) , pp. , Decision tree ensemble-based wafer map failure pattern recognition based on Radon transform-based features, IEEE Transactions on Semiconductor Manufacturing 31 (2) (2018) 250 – 257, 10. 12126. "Wafer defect patterns recognition based on OPTICS and multi-label classification. kg bw gy pz ty jl ct gg qx zp